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STC
FEATURES
Very Low Power/Voltage CMOS SRAM 128K X 16 bit
STC62WV12816
* Wide Vcc operation voltage : 2.4V ~ 5.5V * Very low power consumption : Vcc = 3.0V C-grade: 29mA (@55ns) operating current I -grade: 30mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 0.3uA(Typ.) CMOS standby current Vcc = 5.0V C-grade: 60mA (@55ns) operating current I -grade: 62mA (@55ns) operating current C-grade: 53mA (@70ns) operating current I -grade: 55mA (@70ns) operating current 1.0uA(Typ.) CMOS standby current * High speed access time : -55 55ns -70 70ns * Automatic power down when chip is deselected * Three state outputs and TTL compatible
* Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE and OE options * I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The STC62WV12816 is a high performance , very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.3uA at 3.0V /25oC and maximum access time of 55ns at 3.0V / 85oC. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable(OE) and three-state output drivers. The STC62WV12816 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The STC62WV12816 is available in DICE form , JEDEC standard 44-pin TSOP Type II package and 48-ball BGA package. SPEED
( ns )
55ns: 3.0~5.5V 70ns: 2.7~5.5V
PRODUCT FAMILY
PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE
( ICCSB1, Max ) Vcc=3.0V
POWER DISSIPATION STANDBY Operating
( ICC, Max )
Vcc=5.0V
PKG TYPE DICE TSOP2-44 BGA-48-0608 DICE TSOP2-44 BGA-48-0608
Vcc=3.0V 70ns
Vcc=5.0V 70ns
STC62WV12816DC STC62WV12816EC +0 O C to +70 O C STC62WV12816AC STC62WV12816DI STC62WV12816EI -40 O C to +85 O C STC62WV12816AI
2.4V ~5.5V
55/70
3.0uA
10uA
24mA
53mA
2.4V ~ 5.5V
55/70
5.0uA
30uA
25mA
55mA
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
BLOCK DIAGRAM
A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC
A8 A13 A15
62WV12816EC 62WV12816EI
A16 A14 A12 A7 A6 A5 A4
Address Input Buffer
20
1024
Row Decoder
Memory Array 1024 x 2048
2048 DQ0 16
1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 N.C.
2 OE UB D10 D11 D12 D13 N.C. A8
3 A0 A3 A5 N.C. N.C. A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE D1 D3 D4 D5 WE A11
6 N.C. D0 D2 VCC VSS D6 D7 N.C.
. . . .
DQ15
. . . .
Data Input Buffer
16
Column I/O
Write Driver
Sense Amp
128
16
Data Output
16
Buffer
Column Decoder
CE WE OE UB
LB
14
Control
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Vcc Gnd
STC International Limited. reserves the right to modify document contents without notice.
R0201-STC62WV12816
1
Revision 1.1 Jan. 2004
STC
PIN DESCRIPTIONS
STC62WV12816
Name
A0-A16 Address Input CE Chip Enable Input
Function
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc
Gnd
Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply
Ground
TRUTH TABLE
MODE
Not selected (Power Down)
Output Disabled
CE H
X
L L
WE
X
X
X H
OE
X
X
X H
LB
X
H
H X
UB
X
H
H X
D0~D7
High Z
High Z
High Z High Z
D8~D15
High Z
High Z High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
ICCSB , ICCSB1
ICCSB , ICCSB1 ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
Read L H L
L
L
H
L
L
H
Dout
High Z
Dout
Din
X
Din
H
L
L
Write
L
L
X
H
L
R0201-STC62WV12816
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Revision 1.1 Jan. 2004
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
STC
STC62WV12816
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70 O C -40 C to +85 C
O O
Vcc
2.4V ~ 5.5V 2.4V ~ 5.5V
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to +
PARAMETER NAME
VIL
VIH
IIL
ILO
85oC
)
MIN.
-0.5
2.0
2.2
--Vcc =3.0V
PARAMETER
Guaranteed Input Low (3) Voltage
Guaranteed Input High (3) Voltage
Input Leakage Current
Output Leakage Current
TEST CONDITIONS
Vcc =3.0V
Vcc =5.0V
Vcc =3.0V
Vcc =5.0V
Vcc = Max, VIN = 0V to Vcc
Vcc = Max,CE = VIH or OE = VIH, VI/O = 0V to Vcc
Vcc = Max, IOL = 2.0mA
TYP. (1)
-----
MAX.
0.8
Vcc+0.3
1
1
UNITS
V
V
uA
uA
VOL
Output Low Voltage
Vcc =5.0V
Vcc =3.0V
--
--
0.4
V
VOH
Output High Voltage
Operating Power Supply Current
Standby Current-TTL
Vcc = Min, IOH = -1.0mA
CE = VIL, (2) IDQ = 0mA, F = Fmax
CE=VIH IDQ = 0mA
CEVcc-0.2V, VINVcc-0.2V or VIN0.2V
Vcc =5.0V
Vcc =3V
Vcc =5V
2.4
--
-25
55
0.5
V
ICC
(5)
70ns
70ns
--
--
mA
Vcc =3.0V
-Vcc =5.0V
Vcc =3.0V
Vcc =5.0V --
ICCSB
-1.0
0.3
1.0
mA
5
30
ICCSB1
(4)
Standby Current-CMOS
uA
1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC. 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4.IccsB1_Max. is 3uA / 10uA at Vcc=3V / 5V and TA=70oC. 5. Icc_Max. is 30mA(@3V) / 62mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
VDR
(3)
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
TEST CONDITIONS
CE Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V CE Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V See Retention Waveform
MIN.
1.5 -0 TRC
(2)
TYP. (1)
-0.1 ---
MAX.
-1.0 ---
UNITS
V uA ns ns
ICCDR tCDR tR
1. Vcc = 1.5V, TA = + 25 C R0201-STC62WV12816
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.7uA at TA=70oC. Revision 1.1 Jan. 2004
3
STC
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
STC62WV12816
VDR 1.5V
Vcc
VIH
Vcc
Vcc
t CDR
CE Vcc - 0.2V
tR
VIH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CL = 100pF+1TTL CL = 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
MIN. TYP. MAX.
tAVAX tAVQV tELQV tBA tGLQV t E1LQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA tACS tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
55 -(CE) (LB,UB) (CE) (LB,UB) (CE) (LB,UB) ---10 10 5 ---10
-------------
-55 55 30 30 ---30 30 25 --
70 ----10 10 5 ---10
-------------
-70 70 35 35 ---35 35 30 --
NOTE : 1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-STC62WV12816
4
Revision 1.1 Jan. 2004
STC
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
STC62WV12816
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2
(1,3,4)
CE
t ACS t BA
LB,UB
t BE
D OUT
t
(5) CLZ
t BDO
t
CHZ
(5)
READ CYCLE3
(1,4)
t RC
ADDRESS
t
OE
AA
t OE
CE
t OH
t OLZ t CLZ
(5)
t
ACS
t OHZ (5) (1,5) t CHZ t BA
LB,UB
t BE
D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested.
t BDO
R0201-STC62WV12816
5
Revision 1.1 Jan. 2004
STC
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC PARAMETER NAME
PARAMETER NAME
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
STC62WV12816
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ
tWHOX
t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ
t OW
55
(CE)
-------------
-------25
--25
--
70
70
0
70
35
0
30
-30
0
-5
-------------
-------30
--30
--
55
0
55
30
0
25
-25
0
-5
(CE,WE)
(LB,UB)
NOTE : 1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
t WR
OE
(3)
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t
t DW
DH
D IN
R0201-STC62WV12816
6
Revision 1.1 Jan. 2004
STC
WRITE CYCLE2 (1,6)
STC62WV12816
t WC
ADDRESS
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
t WR t WP
(2)
(3)
t AS
(4,10)
t WHZ
D OUT
t t DW t
OW
(7)
(8)
DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write.
R0201-STC62WV12816
7
Revision 1.1 Jan. 2004
STC
ORDERING INFORMATION
STC62WV12816
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 D: DICE
STC62WV12816 X X
Z
Note: STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8)
R0201-STC62WV12816
E1
8
Revision 1.1 Jan. 2004
STC
PACKAGE DIMENSIONS
STC62WV12816
TSOP2-44
R0201-STC62WV12816
9
Revision 1.1 Jan. 2004

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